exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 fax (510) 668-7017 www.exar.com xr advanced confidential XRT95L53 ex tend ar-48m product brief oc-48 ethernet/sonet multi-service framer processor february 2005 rev. p 1.0.0 general description extendar 48m (XRT95L53) is a highly integrated oc- 48/stm-16, quad oc-12/stm-4 & oc-3/stm-1 multi-protocol framer processor. this device combines standard oc-48/stm-16, quad oc-12/ stm-4, oc-3/stm-1 sonet framer functions with a flexible packet interface as well as a range of framing and encapsulation techniques integrated on a single chip. extendar 48m supports generic framing procedure (gfp) in combination with virtual concatenation & lcas, laps, pos, atm and ds3 capabilities configurable on a per-channel basis. extendar 48m is the industry's first device to integrate 48 ds3/fractional ds3 framers on a single chip. extendar 48m, in addition to the sonet oc- 48/oc-12/oc-3 interfaces, supports oif compliant spi-3 interface with optional support for exar's proprietary g-header interface. using this industry first g-header interface, extendar 48m provides framing and encapsulation support for rpr, mpls or proprietary client data that need to be transported over sonet. the unique combination of flexible packet framing and encapsulation features combined with optimal sonet transport capabilities make extendar 48m an ideal solution for multi-service sonet transport, core as well as dwdm systems. applications ? multi-service provisioning platforms (mspps) ? sonet/sdh add/drop and terminal multiplexers ? ethernet over sonet platforms (mtu/mdu) ? l2/l3 switches & routers key features ? system-side interfaces single oif compliant spi-3 interface with optional support for g-header interface oc-12/stm-4 serdes interface (4x1- bit@622mhz) ? line-side interfaces working and protect oc-48/stm-16 serdes interfaces (4-bit@622mhz) - supports tfi-5 interface quad oc-12/stm-4/oc-3/stm-1 serdes interfaces (4x1-bit@622mhz/155mhz) ? support for flexible mapping of client data on a per channel basis into optimal sonet/sdh payloads using frame-based gfp (gfp -f) maps ethernet data into sonet/sdh payloads using gfp maps ppp frames into sonet/sdh payloads using gfp -f supports gfp mapping of rpr, mpls or proprietary client data using the g-header interface supports add/drop of client management frames from/to the microprocessor interface ? supports a g-header interface in order to effectively map rpr, mpls or proprietary client data over sonet compatible with oif compliant spi-3 interface performs g-header encapsulation/de- capsulation g-header interface can be optionally disabled ? support for contiguous pointer-based concatenation for higher order paths supports mapping of gigabit ethernet to sts- 48c/au4-16c, sts12c/au4-16c or sts3c/ au4 or sts-1/au3 ? support for a spi-3 interface with up to 256 logical sub-channels and individual channel flow control ? support for high order and low order virtual concatenation with optional link capacity adjustment scheme (lcas) supports flexible mapping of multi-protocol traffic into standards based high order virtual concatenation channels of sts-3c-xv/vc-4-xv as well as sts-1-xv/vc-3-xv supports mapping of multi-protocol traffic into standards based low order virtual concatenation channels of vt6/vt2/vt1.5 supports a total of 64 virtual concatenation groups (vcg's) supports link capacity adjustment scheme per itu-t g.7042 provides up to 256 ms of differential delay compensation using external sdram interface ? terminates and processes section, line and path overhead on oc-48/stm-16, oc-12/stm-4 and oc-3/stm-1 interfaces support for extensive performance monitoring on the sonet/sdh interfaces ? support for on-chip sts-1 cross-connect between the oc-12 add/drop interface and the lineside interfaces ? support for upsr and 1+1 linear automatic protection switching preliminary
XRT95L53 ex tend ar-48m advanced confidential xr oc-48 ethernet/sonet multi-service framer processor rev. p 1.0.0 2 ? supports mapping of data using pos/hdlc framing into sonet/sdh in accordance with rfc2615 & ietf 1662 optionally supports ppp/bcp (bridging control protocol) encapsulation performs atm cell de-lineation and maps atm packets into sonet/sdh using pos/hdlc ? support for 48 ds3 and sub-rate ds3 framers on-chip maps/de-maps ds3 signals into sonet/sdh payloads supports extensive performance monitoring on ds3 data integrated fractional ds3/t3 and scrambling functions ? supports mapping of ethernet data over sdh using laps framing according to itu-t x.86 ? supports a 32 bit micro-processor interface for management, configuration, gathering extended statistics and providing interrupts for alarm processing ? supports performance monitoring and alarms as required by gr.253, g.707 and ansi t1.105 f igure 1. XRT95L53 ex tend ar-48m b lock d iagram ordering information p art n umber p ackage t ype o perating t emperature r ange XRT95L53 pbga 780 -40c to 85c sts-48 4-bit @622mhz 4xsts-12/sts-3 oc-48 serdes 4x oc-12 serdes section/line/ toh processor section/line/ toh processor pointer proc. sts-1 path overhead processor and cross connect gfp laps ppp atm gfp laps ppp atm vc lcas vc lcas jtag interface overhead add/drop bus 32 bit uprocessor interface sdram interface ds3/ sub-rate ds3 framers ds3/ sub-rate ds3 framers sts-12 (add/drop port) 4x1-bit@622mhz spi-3 interface pos-phy 3 g-header interface preliminary
xr advanced confidential XRT95L53 ex tend ar-48m rev. p 1.0.0 oc-48 ethernet/sonet multi-service framer processor 3 t able 1: k ey f eature , a dvantage and b enefits m atrix e xtendar 48m f eatures a dvantage e xtendar 48m b enefits 1 supports a range of flexible encapsu - lation & framing features including gfp -f, laps, ppp/hdlc, bcp and atm supports the latest standards of gfp - f and -t and provides flexibility of dif - ferent encapsulation /framing features on a per channel basis supports a wide range of framing and encapsulation features ensuring the effective mapping of different types of client data 2 supports 48 ds3 and sub-rate ds3 framers on a single chip supports a unique combination of ds3 framer functionality coupled with advanced packet encapsulation and sonet framing functions in a single chip high level of integration reduces the total system bom cost single device enables multiple applica - tions 3 supports high order and low order virtual concatenation capability for 64 vc channels with lcas supports both ho order virtual con - catenation as well as vt mapping sup - port in a single chip. enables the optimal utilization of sonet bandwidth for various types of client data as well as ensures the dynamic allocation of bandwidth to meet service-level requirements. 4 supports a proprietary g-header interface compatible with oif compli - ant spi-3 interface enables support for rpr , mpls and other proprietary client data types that need to be optimally transported over sonet. promotes flexibility and ease of use spanning multiple applications f igure 2. a pplications ex tend ar48 multi-protocol framer processor ex calib ar lite 24 fe spi-3 ethernet aggregator 91l80 oc-48 xcvr fe/ge phy fe/ge phy fe/ge phy sgmii sgmii sgmii backplane interface 4 bit 622mhz 2.5g serial l2 ethernet switch 8 ge fe/ge phy fe/ge phy sgmii sgmii ex calib ar lite 24 fe spi-3 ethernet aggregator e/fe/ge phy e/fe/ge phy e/fe/ge phy sgmii sgmii sgmii spi-3 spi-3 4 ge ex tend ar48 multi-protocol framer processor 91l80 oc-48 xcvr backplane interface 4 bit 622mhz 2.5g serial spi-3 npu/ asic ex tend ar48 multi-protocol framer processor 91l80 oc-48 xcvr backplane interface 4 bit 622mhz 2.5g serial oc-48 ethernet over sonet transport aggregator card spi-3 ex tend ar48 multi-protocol framer processor 91l80 oc-48 xcvr oc-48 sfp optics 4 bit @ 622mhz 2.5g serial npu spi-3 "glue logic" fpga backplane oc-48 ds1 channelized framer sts-12 (telecom bus) spi-3 oc-48 sonet/sdh card with ds1 channelization preliminary
XRT95L53 ex tend ar-48m advanced confidential xr oc-48 ethernet/sonet multi-service framer processor rev. p 1.0.0 4 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2005 exar corporation datasheet february 2005. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history r evision # d ate d escription a1.0.0 february 2005 initial release. preliminary
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